CPE 626 Advanced VLSI Design, Fall 2004
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HOMEWORK #1

Issued: 9/8/2004
Dues: 9/22/2004


This homework offers hands-on-experience in VHDL modeling and 
introduces features, tools, and the design flow in Xilinx ISE.


1. (85 points) 
Model, verify, and implement a soft IP (Intellectual Property) core
for a rudimentary microprocessor Mu0, described in class.
The model is to be implemented on a Xilinx device 
(Spartan2, Spartan3, or Virtex family).

Deliverables: 
0) Up to 2 pages of description
1) VHDL model and testbenches
2) Results of simulation (functional and post-place & route)
3) Synthesis report
4) Power report
5) Floorplan report

2. (30 points) 
Adapt VHDL model from 1) to utilize
on-chip BRAMs for the main memory.